PD(Backend) Jobs: Floorplan, P&R, ECO, Physical verfication (DRC/LVS/DFM .. etc), IR_DROP check
PD(Backend) tools: ICC2(Major) or Innovus, STAR_RCXT, Calibre, Redhawk
- Hands on experience in some aspects of design flows such as floor planning, placement optimization, clock tree synthesis, routing, crosstalk avoidance and physical verification
- Experience in block level/full chip Physical Design activities.
- Basic Knowledge on VLSI and basic Knowledge on Timing.
- Hands on Experience in areas of physical verification (DRC/LVS/ERC/ANT) using Calibre or equivalent.
- Proficiency in Tcl and Perl scripting is essential.
- Hands on Experience in ICC, Innovus or equivalent.
- Experience on PrimeTime, StarRC-XT, Formality, Redhawk or equivalent will be preferred.
- Self-motivated team player with strong problem-solving skills that can collaborate with various teams to achieve design goals.
- Responsible for floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing analysis, Power and Signal Integrity Analysis and
- Physical Verification of Low power and high frequency designs.
- Extensive experience and detailed knowledge in Cadence or Synopsys or Physical Design Tools
- Desired skills- Provide technical guidance, Leadership quality
- Should have been familiarity with process nodes ( 7nm/14nm/16nm/28nm )?
- Excellent written and verbal communication skills required